Adaptive Method for Minimization of Power Consumption in Sequential Circuits Through DVS and Error Prediction


This paper presents Adaptive methodology to compensate the On Chip Variations (OCV), aging effect and manufacturing uncertainties in sub threshold circuits. “Canary flip-flop (FF),” is used to predict the timing violations. A FSM, 4-bit Counter, in CMOS 90nm technology whose performance is controlled by automatically changing voltage levels (DVS) as per the timing error prediction. In addition, the voltage supply is further scaled down if no timing error is predicted within certain time period to save more power at different PVT conditions. Back end simulation results shows, the design under observation with this technique can compensate process, supply voltage and temperature instability with an efficient power savings of nearly 40% with respect to the conventional worst case design with timing margins approach. Here we also demonstrate how to define the delay of delay chain during the design phase itself.


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